Issued Patents 2005
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6961916 | Placement method for integrated circuit design using topo-clustering | Majid Sarrafzadeh, Lawrence Pileggi, Feroze P. Taraporevala, Abhijeet Chakraborty, Gary K. Yeap +4 more | 2005-11-01 |
| 6874135 | Method for design validation using retiming | Aarti Gupta, Pranav Ashar | 2005-03-29 |