Issued Patents 2005
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6963941 | High speed bus topology for expandable systems | — | 2005-11-08 |
| 6961259 | Apparatus and methods for optically-coupled memory systems | Kevin J. Ryan | 2005-11-01 |
| 6934785 | High speed interface with looped bus | Roy Greeff, David K. Ovard | 2005-08-23 |
| 6928019 | Semiconductor device with self refresh test mode | — | 2005-08-09 |
| 6898726 | Memory system that sets a predetermined phase relationship between read and write clock signals at a bus midpoint for a plurality of spaced device locations | — | 2005-05-24 |
| 6889357 | Timing calibration pattern for SLDRAM | Brent Keeth, Brian Johnson, Paul Fuller | 2005-05-03 |
| 6871253 | Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection | Roy Greeff, David K. Ovard | 2005-03-22 |
| 6856567 | Semiconductor device with self refresh test mode | — | 2005-02-15 |
| 6845460 | Device and system for adjusting delay in a data path based on comparison of data from a latch and data from a register | Kevin J. Ryan, Joseph M. Jeddeloh | 2005-01-18 |
| 6837731 | Locking assembly for securing a semiconductor device to a carrier substrate | David J. Corisis, Jerry M. Brooks | 2005-01-04 |