Issued Patents 2005
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6981100 | Synchronous DRAM with selectable internal prefetch size | Christopher Johnson | 2005-12-27 |
| 6977655 | Dual mode DDR SDRAM/SGRAM | — | 2005-12-20 |
| 6963949 | Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus | — | 2005-11-08 |
| 6961259 | Apparatus and methods for optically-coupled memory systems | Terry R. Lee | 2005-11-01 |
| 6948027 | Method and system for using dynamic random access memory as cache memory | Brent Keeth, Brian M. Shirley, Charles H. Dennison | 2005-09-20 |
| 6941415 | DRAM with hidden refresh | — | 2005-09-06 |
| 6907493 | Memory device interface | — | 2005-06-14 |
| 6895474 | Synchronous DRAM with selectable internal prefetch size | Christopher Johnson | 2005-05-17 |
| 6862654 | Method and system for using dynamic random access memory as cache memory | Brent Keeth, Brian M. Shirley, Charles H. Dennison | 2005-03-01 |
| 6851016 | System latency levelization for read data | Jeffery W. Janzen, Brent Keeth, Troy A. Manning, Brian Johnson | 2005-02-01 |
| 6845460 | Device and system for adjusting delay in a data path based on comparison of data from a latch and data from a register | Terry R. Lee, Joseph M. Jeddeloh | 2005-01-18 |
| 6842393 | Method for selecting one or a bank of memory devices | Brent Keeth | 2005-01-11 |