Issued Patents 2005
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6969633 | Lower electrode isolation in a double-wide trench and method of making same | — | 2005-11-29 |
| 6967146 | Isolation region forming methods | David Dickerson, Richard H. Lane, Kunal R. Parekh, Mark Fischer, John K. Zahurak | 2005-11-22 |
| 6948027 | Method and system for using dynamic random access memory as cache memory | Brent Keeth, Brian M. Shirley, Kevin J. Ryan | 2005-09-20 |
| 6939799 | Method of forming a field effect transistor and methods of forming integrated circuitry | — | 2005-09-06 |
| 6924190 | Use of gate electrode workfunction to improve DRAM refresh | — | 2005-08-02 |
| 6919578 | Utilizing atomic layer deposition for programmable device | Tyler Lowrey | 2005-07-19 |
| 6897542 | Semiconductor assemblies | — | 2005-05-24 |
| 6894332 | Apparatus for reducing electrical shorts from the bit line to the cell plate | Kunal R. Parekh, Jeffrey W. Honeycutt | 2005-05-17 |
| 6882017 | Field effect transistors and integrated circuitry | — | 2005-04-19 |
| 6869883 | Forming phase change memories | Chien-Chih Chiang, Tyler Lowrey | 2005-03-22 |
| 6862654 | Method and system for using dynamic random access memory as cache memory | Brent Keeth, Brian M. Shirley, Kevin J. Ryan | 2005-03-01 |
| 6858507 | Graded LDD implant process for sub-half-micron MOS devices | Aftab Ahmad | 2005-02-22 |
| 6855628 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry | — | 2005-02-15 |