Issued Patents 2005
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6941494 | Built-in test for multiple memory circuits | Alexander E. Andreev, Lav D. Ivanovic | 2005-09-06 |
| 6941533 | Clock tree synthesis with skew for memory devices | Alexander E. Andreev, Ivan Pavisic | 2005-09-06 |
| 6848094 | Netlist redundancy detection and global simplification | Alexander E. Andreev | 2005-01-25 |