Issued Patents 2005
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6941314 | User selectable editing protocol for fast flexible search engine | Ranko Scepanovic | 2005-09-06 |
| 6941533 | Clock tree synthesis with skew for memory devices | Igor Vikhliantsev, Ivan Pavisic | 2005-09-06 |
| 6941494 | Built-in test for multiple memory circuits | Igor Vikhliantsev, Lav D. Ivanovic | 2005-09-06 |
| 6934733 | Optimization of adder based circuit architecture | Sergej B. Gashkov, Aiguo Lu | 2005-08-23 |
| 6901573 | Method for evaluating logic functions by logic circuits having optimized number of and/or switches | Andrey Nikitin | 2005-05-31 |
| 6886088 | Memory that allows simultaneous read requests | Egor A. Andreev, Anatoli Bolotov, Ranko Scepanovic | 2005-04-26 |
| 6848094 | Netlist redundancy detection and global simplification | Igor Vikhliantsev | 2005-01-25 |
| 6842750 | Symbolic simulation driven netlist simplification | Ranko Scepanovic | 2005-01-11 |