Issued Patents 2005
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6958545 | Method for reducing wiring congestion in a VLSI chip design | Pooja M. Kotecha, Ruchir Puri, Louise H. Trevillyan, Adam P. Matheny | 2005-10-25 |
| 6915496 | Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique | Charles J. Alpert, Chong-Nuen Chu, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap +1 more | 2005-07-05 |
| 6898774 | Buffer insertion with adaptive blockage avoidance | Charles J. Alpert, Jiang Hu, Stephen T. Quay | 2005-05-24 |