Issued Patents 2005
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6968306 | Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model | Anirudh Devgan, Chandramouli V. Kashyap | 2005-11-22 |
| 6950996 | Interconnect delay and slew metrics based on the lognormal distribution | Anirudh Devgan, Chandramouli V. Kashyap, Ying Liu | 2005-09-27 |
| 6915361 | Optimal buffered routing path constructions for single and multiple clock domains systems | Soha Hassoun | 2005-07-05 |
| 6915496 | Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique | Chong-Nuen Chu, Rama Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap +1 more | 2005-07-05 |
| 6898774 | Buffer insertion with adaptive blockage avoidance | Rama Gopal Gandham, Jiang Hu, Stephen T. Quay | 2005-05-24 |
| 6868533 | Method and system for extending delay and slew metrics to ramp inputs | Anirudh Devgan, Chandramouli V. Kashyap, Ying Liu | 2005-03-15 |