Issued Patents 2005
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6966046 | CMOS tapered gate and synthesis method | Brian W. Curran, Lisa Bryant Lacey, Gregory A. Northrop, Leon Stok | 2005-11-15 |
| 6958545 | Method for reducing wiring congestion in a VLSI chip design | Pooja M. Kotecha, Rama Gopal Gandham, Louise H. Trevillyan, Adam P. Matheny | 2005-10-25 |