Issued Patents 2005
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6872630 | Using V-groove etching method to reduce alignment mark asymmetric damage in integrated circuit process | — | 2005-03-29 |
| 6838217 | Define overlay dummy pattern in mark shielding region to reduce wafer scale error caused by metal deposition | Szu-Ping Chen, Chin-Chuan Hsieh | 2005-01-04 |