PG

Prakash Gopalakrishnan

CS Cadence Design Systems: 1 patents #18 of 77Top 25%
📍 Wayne, NJ: #5 of 32 inventorsTop 20%
🗺 New Jersey: #1,157 of 4,577 inventorsTop 30%
Overall (2005): #120,914 of 245,428Top 50%
1
Patents 2005

Issued Patents 2005

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6874133 Integrated circuit design layout compaction method Rob A. Rutenbar, Elias Lee Fallon 2005-03-29