EF

Elias Lee Fallon

CS Cadence Design Systems: 2 patents #13 of 77Top 20%
📍 Washington, PA: #2 of 30 inventorsTop 7%
🗺 Pennsylvania: #377 of 4,560 inventorsTop 9%
Overall (2005): #57,305 of 245,428Top 25%
2
Patents 2005

Issued Patents 2005

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6918102 Method and apparatus for exact relative positioning of devices in a semiconductor circuit layout Rob A. Rutenbar, Regis Colwell 2005-07-12
6874133 Integrated circuit design layout compaction method Prakash Gopalakrishnan, Rob A. Rutenbar 2005-03-29