Issued Patents 2004
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6812116 | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance | Chien-Chao Huang, Yee-Chia Yeo, Chun-Chieh Lin, Chenming Hu | 2004-11-02 |
| 6784071 | Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement | Haur-Ywh Chen, Yi-Ling Chan, Fu-Liang Yang, Chenming Hu | 2004-08-31 |
| 6674130 | High performance PD SOI tunneling-biased MOSFET | Yi-Ling Chan, You-Lin Chu, Hou-Yu Chen, Fu-Liang Yang, Chenming Hu | 2004-01-06 |