Issued Patents 2004
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6830953 | Suppression of MOSFET gate leakage current | Yee-Chia Yeo | 2004-12-14 |
| 6812116 | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance | Chien-Chao Huang, Yee-Chia Yeo, Kuo-Nan Yang, Chun-Chieh Lin | 2004-11-02 |
| RE38608 | Low-voltage punch-through transient suppressor employing a dual-base structure | Bin Yu, Ya-Chin King, Jeffrey T. Pohlman, Rita Trivedi | 2004-10-05 |
| 6794234 | Dual work function CMOS gate technology based on metal interdiffusion | Igor Polishchuk, Pushkar Ranade, Tsu-Jae King | 2004-09-21 |
| 6784071 | Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement | Haur-Ywh Chen, Yi-Ling Chan, Kuo-Nan Yang, Fu-Liang Yang | 2004-08-31 |
| 6720619 | Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices | Hao Chen, Yee-Chia Yeo, Fu-Liang Yang | 2004-04-13 |
| 6674130 | High performance PD SOI tunneling-biased MOSFET | Kuo-Nan Yang, Yi-Ling Chan, You-Lin Chu, Hou-Yu Chen, Fu-Liang Yang | 2004-01-06 |