Issued Patents 2004
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6834378 | System on a chip bus with automatic pipeline stage insertion for timing closure | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Richard Gerard Hofmann, Barry Joe Wolford | 2004-12-21 |
| 6826656 | Reducing power in a snooping cache based multiprocessor environment | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Richard Gerard Hofmann, Barry Joe Wolford | 2004-11-30 |
| 6826747 | System and method for tracing program instructions before and after a trace triggering event within a processor | Victor Roberts Augsburg, Jeffrey Todd Bridges, Thomas Kevin Collopy, James Norris Dieffenderfer | 2004-11-30 |
| 6816962 | Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions | Victor Roberts Augsburg, Jeffrey Todd Bridges, Rodney Wayne Smith, Thomas Philip Speier | 2004-11-09 |
| 6807608 | Multiprocessor environment supporting variable-sized coherency transactions | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Richard Gerard Hofmann, Barry Joe Wolford | 2004-10-19 |