Issued Patents 2004
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6834378 | System on a chip bus with automatic pipeline stage insertion for timing closure | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Thomas Andrew Sartorius, Barry Joe Wolford | 2004-12-21 |
| 6826656 | Reducing power in a snooping cache based multiprocessor environment | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Thomas Andrew Sartorius, Barry Joe Wolford | 2004-11-30 |
| 6823411 | N-way psuedo cross-bar having an arbitration feature using discrete processor local busses | Barry Joe Wolford | 2004-11-23 |
| 6807608 | Multiprocessor environment supporting variable-sized coherency transactions | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Thomas Andrew Sartorius, Barry Joe Wolford | 2004-10-19 |
| 6772254 | Multi-master computer system with overlapped read and write operations and scalable address pipelining | Jason Michael Hopp, Peter Dean LaFauci, Dennis Charles Wilkerson | 2004-08-03 |