Issued Patents 2004
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6810515 | Process of restructuring logics in ICs for setup and hold time optimization | Aiguo Lu, Andrej A. Zolotykh, Elyar E. Gasanov | 2004-10-26 |
| 6804811 | Process for layout of memory matrices in integrated circuits | Alexander E. Andreev, Ranko Scepanovic | 2004-10-12 |
| 6760896 | Process layout of buffer modules in integrated circuits | Alexander E. Andreev, Ranko Scepanovic | 2004-07-06 |
| 6757877 | System and method for identifying and eliminating bottlenecks in integrated circuit designs | Robert Stenberg | 2004-06-29 |
| 6757881 | Power routing with obstacles | Alexandre Andreev, Lav D. Ivanovic | 2004-06-29 |
| 6701493 | Floor plan tester for integrated circuit design | Elyar E. Gasanov, Andrej A. Zolotykh, Aiguo Lu | 2004-03-02 |