Issued Patents 2004
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6810515 | Process of restructuring logics in ICs for setup and hold time optimization | Ivan Pavisic, Andrej A. Zolotykh, Elyar E. Gasanov | 2004-10-26 |
| 6701493 | Floor plan tester for integrated circuit design | Elyar E. Gasanov, Andrej A. Zolotykh, Ivan Pavisic | 2004-03-02 |
| 6691283 | Optimization of comparator architecture | Sergej B. Gashkov, Alexander E. Andreev | 2004-02-10 |