Issued Patents 2004
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6810515 | Process of restructuring logics in ICs for setup and hold time optimization | Aiguo Lu, Ivan Pavisic, Elyar E. Gasanov | 2004-10-26 |
| 6701493 | Floor plan tester for integrated circuit design | Elyar E. Gasanov, Ivan Pavisic, Aiguo Lu | 2004-03-02 |
| 6701503 | Overlap remover manager | Andrey Nikitin, Elyar E. Gasanov | 2004-03-02 |
| 6681373 | Method and apparatus for dynamic buffer and inverter tree optimization | Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev | 2004-01-20 |