FD

Frank Distler

CS Cadence Design Systems: 1 patents #23 of 106Top 25%
📍 Münster, VT: #1 of 1 inventorsTop 100%
Overall (2004): #224,382 of 270,089Top 85%
1
Patents 2004

Issued Patents 2004

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6782501 System for reducing test data volume in the testing of logic products L. Farnsworth, Andrew Ferko, Brion Keller, Bernd Koenemann 2004-08-24