AF

Andrew Ferko

CS Cadence Design Systems: 1 patents #23 of 106Top 25%
📍 Waterbury, VT: #1 of 6 inventorsTop 20%
🗺 Vermont: #171 of 538 inventorsTop 35%
Overall (2004): #261,493 of 270,089Top 100%
1
Patents 2004

Issued Patents 2004

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6782501 System for reducing test data volume in the testing of logic products Frank Distler, L. Farnsworth, Brion Keller, Bernd Koenemann 2004-08-24