Issued Patents 2003
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6544846 | Method of manufacturing a single electron resistor memory device | Leonard Forbes | 2003-04-08 |
| 6541362 | Methods of forming semiconductor structures | Leonard Forbes, Luan C. Tran | 2003-04-01 |
| 6541859 | Methods and structures for silver interconnections in integrated circuits | Leonard Forbes, Paul A. Farrar | 2003-04-01 |
| 6539490 | Clock distribution without clock delay or skew | Leonard Forbes | 2003-03-25 |
| 6534855 | Wireless communications system and method of making | Leonard Forbes | 2003-03-18 |
| 6535101 | Low loss high Q inductor | Leonard Forbes | 2003-03-18 |
| 6534420 | Methods for forming dielectric materials and methods for forming semiconductor devices | Leonard Forbes | 2003-03-18 |
| 6531945 | Integrated circuit inductor with a magnetic core | Leonard Forbes | 2003-03-11 |
| 6531727 | Open bit line DRAM with ultra thin body transistors | Leonard Forbes | 2003-03-11 |
| 6526191 | Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same | Joseph E. Geusic, Leonard Forbes | 2003-02-25 |
| 6518615 | Method and structure for high capacitance memory cells | Joseph E. Geusic, Leonard Forbes | 2003-02-11 |
| 6514820 | Method for forming single electron resistor memory | Leonard Forbes | 2003-02-04 |
| 6514828 | Method of fabricating a highly reliable gate oxide | Leonard Forbes | 2003-02-04 |
| 6512695 | Field programmable logic arrays with transistors with vertical gates | Leonard Forbes | 2003-01-28 |
| 6504224 | Methods and structures for metal interconnections in integrated circuits | Leonard Forbes, Paul A. Farrar | 2003-01-07 |
| 6504201 | Memory cell having a vertical transistor with buried source/drain and dual gates | Wendell P. Noble, Leonard Forbes | 2003-01-07 |