Issued Patents 2003
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6664600 | Graded LDD implant process for sub-half-micron MOS devices | Aftab Ahmad | 2003-12-16 |
| 6649928 | Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby | — | 2003-11-18 |
| 6646297 | Lower electrode isolation in a double-wide trench | — | 2003-11-11 |
| 6620672 | SOI DRAM with buried capacitor under the digit lines utilizing a self aligning penetrating storage node contact formation | John K. Zahurak | 2003-09-16 |
| 6605527 | Reduced area intersection between electrode and programming element | Alice Wang, Patel Kanaiyalal Chaturbhai, Jenn C. Chow | 2003-08-12 |
| 6605532 | Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same | Kunal R. Parekh, Mark Fischer | 2003-08-12 |
| 6593176 | METHOD FOR FORMING PHASE-CHANGE MEMORY BIPOLAR ARRAY UTILIZING A SINGLE SHALLOW TRENCH ISOLATION FOR CREATING AN INDIVIDUAL ACTIVE AREA REGION FOR TWO MEMORY ARRAY ELEMENTS AND ONE BIPOLAR BASE CONTACT | — | 2003-07-15 |
| 6593192 | Method of forming a dual-gated semiconductor-on-insulator device | John K. Zahurak, Brent Keeth | 2003-07-15 |
| 6593206 | Isolation region forming methods | David Dickerson, Richard H. Lane, Kunal R. Parekh, Mark Fischer, John K. Zahurak | 2003-07-15 |
| 6573601 | Integrated circuit contact | Trung T. Doan | 2003-06-03 |
| 6552945 | METHOD FOR STORING A TEMPERATURE THRESHOLD IN AN INTEGRATED CIRCUIT, METHOD FOR STORING A TEMPERATURE THRESHOLD IN A DYNAMIC RANDOM ACCESS MEMORY, METHOD OF MODIFYING DYNAMIC RANDOM ACCESS MEMORY OPERATION IN RESPONSE TO TEMPERATURE, PROGRAMMABLE TEMPERATURE SENSING CIRCUIT AND MEMORY INTEGRATED CIRCUIT | Christopher B. Cooper, Ming-Bo Liu, Chris G. Martin, Troy A. Manning, Stephen L. Casper +3 more | 2003-04-22 |
| 6552401 | Use of gate electrode workfunction to improve DRAM refresh | — | 2003-04-22 |
| 6537891 | Silicon on insulator DRAM process utilizing both fully and partially depleted devices | John K. Zahurak | 2003-03-25 |
| RE38049 | Optimized container stacked capacitor dram cell utilizing sacrificial oxide deposition and chemical mechanical polishing | Michael A. Walker | 2003-03-25 |
| 6534781 | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact | — | 2003-03-18 |
| 6524907 | Method of reducing electrical shorts from the bit line to the cell plate | Kunal R. Parekh, Jeffrey W. Honeycutt | 2003-02-25 |
| 6511867 | Utilizing atomic layer deposition for programmable device | Tyler Lowrey | 2003-01-28 |