JP

Jayanthi Pallinti

Lsi Logic: 4 patents #29 of 465Top 7%
🗺 California: #1,459 of 28,521 inventorsTop 6%
Overall (2003): #15,999 of 273,478Top 6%
4
Patents 2003

Issued Patents 2003

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
6607967 Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate Dawn M. Lee, Ronald J. Nagahara 2003-08-19
6586326 Metal planarization system Samuel V. Dunton, Ronald J. Nagahara 2003-07-01
6555475 Arrangement and method for polishing a surface of a semiconductor wafer Ron Nagahara 2003-04-29
6503828 Process for selective polishing of metal-filled trenches of integrated circuit structures Ronald J. Nagahara, James J. Xie, Akihisa Ueno 2003-01-07