DL

Dawn M. Lee

Lsi Logic: 2 patents #67 of 465Top 15%
📍 San Jose, CA: #437 of 2,756 inventorsTop 20%
🗺 California: #4,287 of 28,521 inventorsTop 20%
Overall (2003): #71,053 of 273,478Top 30%
2
Patents 2003

Issued Patents 2003

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6607967 Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate Jayanthi Pallinti, Ronald J. Nagahara 2003-08-19
6531397 Method and apparatus for using across wafer back pressure differentials to influence the performance of chemical mechanical polishing Ronald J. Nagahara 2003-03-11