Issued Patents 2002
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6479859 | Split gate flash memory with multiple self-alignments | Chia-Ta Hsieh, Tai-Fen Lin, Chuang-Ke Yeh, Hung-Cheng Sung, Di-Son Kuo | 2002-11-12 |
| 6468863 | Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof | Chia-Ta Hsieh, Di-Son Kuo, Jake Yeh, Chuan-Li Chang, Sheng-Wei Tsaur | 2002-10-22 |
| 6465836 | Vertical split gate field effect transistor (FET) device | Chrong-Jung Lin, Sheng-Wei Tsao, Di-Son Kuo, Jack Y. Yeh, Chung-Li Chang +1 more | 2002-10-15 |
| 6420233 | Split gate field effect transistor (FET) device employing non-linear polysilicon floating gate electrode dopant profile | Chia-Ta Hsieh, Di-Son Kuo, Jake Yeh, Chung-Li Chang, Chrong-Jung Lin | 2002-07-16 |
| 6417046 | Modified nitride spacer for solving charge retention issue in floating gate memory cell | Ming-Chou Ho, Chang-Song Lin, Chuan-Li Chang, Hsin-Ming Chen, Di-Son Kuo | 2002-07-09 |
| 6403494 | Method of forming a floating gate self-aligned to STI on EEPROM | Di-Son Kuo, Jack Y. Yeh, Chia-Ta Hsieh, Chuan-Li Chang | 2002-06-11 |
| 6387757 | Sacrificial self aligned spacer layer ion implant mask method for forming a split gate field effect transistor (FET) device | Di-Son Kuo, Jake Yeh, Chia-Da Hsieh, Chuan-Li Chang, Sheng-Wei Tsaur | 2002-05-14 |
| 6348382 | Integration process to increase high voltage breakdown performance | Hung-Der Su, Chrong-Jung Lin, Jong Chen | 2002-02-19 |