Issued Patents 2002
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6495880 | Method to fabricate a flash memory cell with a planar stacked gate | Chrong-Jung Lin, Jong Chen, Hung-Der Su | 2002-12-17 |
| 6483159 | Undoped polysilicon as the floating-gate of a split-gate flash cell | Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Juang-Ke Yeh | 2002-11-19 |
| 6479859 | Split gate flash memory with multiple self-alignments | Chia-Ta Hsieh, Tai-Fen Lin, Wen-Ting Chu, Chuang-Ke Yeh, Hung-Cheng Sung | 2002-11-12 |
| 6468863 | Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof | Chia-Ta Hsieh, Jake Yeh, Chuan-Li Chang, Wen-Ting Chu, Sheng-Wei Tsaur | 2002-10-22 |
| 6465841 | Split gate flash memory device having nitride spacer to prevent inter-poly oxide damage | Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Jack Y. Yeh | 2002-10-15 |
| 6465836 | Vertical split gate field effect transistor (FET) device | Chrong-Jung Lin, Sheng-Wei Tsao, Jack Y. Yeh, Wen-Ting Chu, Chung-Li Chang +1 more | 2002-10-15 |
| 6455887 | Nonvolatile devices with P-channel EEPROM device as injector | Yai-Fen Lin, Shiou-Hann Liaw, Jian-Hsing Lee | 2002-09-24 |
| 6441429 | Split-gate flash memory device having floating gate electrode with sharp peak | Chia-Ta Hsieh, Hung-Cheng Sung, Yai-Fen Lin | 2002-08-27 |
| 6437397 | Flash memory cell with vertically oriented channel | Chrong-Jung Lin, Shui-Hung Chen, Jong Chen | 2002-08-20 |
| 6420233 | Split gate field effect transistor (FET) device employing non-linear polysilicon floating gate electrode dopant profile | Chia-Ta Hsieh, Jake Yeh, Chung-Li Chang, Wen-Ting Chu, Chrong-Jung Lin | 2002-07-16 |
| 6417046 | Modified nitride spacer for solving charge retention issue in floating gate memory cell | Ming-Chou Ho, Wen-Ting Chu, Chang-Song Lin, Chuan-Li Chang, Hsin-Ming Chen | 2002-07-09 |
| 6417049 | Split gate flash cell for multiple storage | Hung-Cheng Sung, Chia-Ta Hsieh, Yai-Fen Lin | 2002-07-09 |
| 6410957 | Method of forming poly tip to improve erasing and programming speed in split gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung | 2002-06-25 |
| 6403494 | Method of forming a floating gate self-aligned to STI on EEPROM | Wen-Ting Chu, Jack Y. Yeh, Chia-Ta Hsieh, Chuan-Li Chang | 2002-06-11 |
| 6396112 | Method of fabricating buried source to shrink chip size in memory array | Chia-Ta Hsieh, Jenn Tsao, Yai-Fen Lin, Hung-Cheng Sung | 2002-05-28 |
| 6391719 | Method of manufacture of vertical split gate flash memory device | Chrong-Jung Lin, Shui-Hung Chen | 2002-05-21 |
| 6387757 | Sacrificial self aligned spacer layer ion implant mask method for forming a split gate field effect transistor (FET) device | Wen-Ting Chu, Jake Yeh, Chia-Da Hsieh, Chuan-Li Chang, Sheng-Wei Tsaur | 2002-05-14 |
| 6380035 | Poly tip formation and self-align source process for split-gate flash cell | Hung-Cheng Sung, Chia-Ta Hsieh, Yai-Fen Lin | 2002-04-30 |
| 6380583 | Method to increase coupling ratio of source to floating gate in split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Jack Y. Yeh | 2002-04-30 |
| 6355527 | Method to increase coupling ratio of source to floating gate in split-gate flash | Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Jack Y. Yeh | 2002-03-12 |