Issued Patents 2002
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6453437 | Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation | Rohit Kapur, John A. Waicukauski, Peter Wohl | 2002-09-17 |
| 6434733 | System and method for high-level test planning for layout | Suryanarayana Duggirala, Rohit Kapur | 2002-08-13 |
| 6405355 | Method for placement-based scan-in and scan-out ports selection | Suryanarayana Duggirala, Rohit Kapur | 2002-06-11 |
| 6385750 | Method and system for controlling test data volume in deterministic test pattern generation | Rohit Kapur, John A. Waicukauski, Peter Wohl | 2002-05-07 |