SD

Suryanarayana Duggirala

SY Synopsys: 2 patents #7 of 48Top 15%
📍 San Jose, CA: #402 of 2,494 inventorsTop 20%
🗺 California: #3,859 of 26,763 inventorsTop 15%
Overall (2002): #40,344 of 266,432Top 20%
2
Patents 2002

Issued Patents 2002

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6434733 System and method for high-level test planning for layout Rohit Kapur, Thomas W. Williams 2002-08-13
6405355 Method for placement-based scan-in and scan-out ports selection Rohit Kapur, Thomas W. Williams 2002-06-11