Issued Patents 2002
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6490661 | Maintaining cache coherency during a memory read operation in a multiprocessing computer system | James B. Keller | 2002-12-03 |
| 6473837 | Snoop resynchronization mechanism to preserve read ordering | William A. Hughes, Hebbalalu S. Ramagopal, Stephen M. Conor | 2002-10-29 |
| 6449713 | Implementation of a conditional move instruction in an out-of-order processor | Joel S. Emer, Bruce E. Edwards, Daniel Leibholz, Edward J. McLellan | 2002-09-10 |
| 6446215 | Method and apparatus for controlling power management state transitions between devices connected via a clock forwarded interface | Scott White, Michael T. Clark, Philip E. Madrid | 2002-09-03 |
| 6442677 | Apparatus and method for superforwarding load operands in a microprocessor | Stephan G. Meier, Norbert Juffa | 2002-08-27 |
| 6430639 | Minimizing use of bus command code points to request the start and end of a lock | William Kurt Lewchuk | 2002-08-06 |
| 6427193 | Deadlock avoidance using exponential backoff | William A. Hughes | 2002-07-30 |
| 6424688 | Method to transfer data in a system with multiple clock domains using clock skipping techniques | Teik-Chung Tan, Brian D. McMinn | 2002-07-23 |
| 6405305 | Rapid execution of floating point load control word instructions | Stephan G. Meier, Jeffrey E. Trull, Norbert Juffa | 2002-06-11 |
| 6405304 | Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list | James Arthur Farrell, Sharon Marie Britton, Harry Ray Fair, III, Bruce Gieseke, Daniel Leibholz | 2002-06-11 |
| 6393502 | System and method for initiating a serial data transfer between two clock domains | Philip E. Madrid | 2002-05-21 |
| 6374344 | Methods and apparatus for processing load instructions in the presence of RAM array and data bus conflicts | David A. Webb, James B. Keller | 2002-04-16 |
| 6360314 | Data cache having store queue bypass for out-of-order instruction execution and method for same | David A. Webb, James B. Keller | 2002-03-19 |