Issued Patents 2002
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6473832 | Load/store unit having pre-cache and post-cache queues for low latency load memory operations | Hebbalalu S. Ramagopal, William A. Hughes | 2002-10-29 |
| 6446189 | Computer system including a novel address translation mechanism | Gerald D. Zuraski, Jr., Frederick Daniel Weber, William A. Hughes, Scott White, Michael T. Clark | 2002-09-03 |
| 6430639 | Minimizing use of bus command code points to request the start and end of a lock | Derrick R. Meyer | 2002-08-06 |
| 6415360 | Minimizing self-modifying code checks for uncacheable memory types | William A. Hughes, Gerald D. Zuraski, Jr. | 2002-07-02 |