FJ

Fernand N. Forcier, Jr.

VT Vlsi Technology: 2 patents #12 of 143Top 9%
📍 San Jose, CA: #163 of 1,308 inventorsTop 15%
🗺 California: #1,869 of 17,285 inventorsTop 15%
Overall (1997): #40,983 of 185,788Top 25%
2
Patents 1997

Issued Patents 1997

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
5641988 Multi-layered, integrated circuit package having reduced parasitic noise characteristics Chin-Ching Huang, Sang S. Lee, Ramachandra A. Rao 1997-06-24
5625225 Multi-layered, integrated circuit package having reduced parasitic noise characteristics Chin-Ching Huang, Sang S. Lee, Ramachandra A. Rao 1997-04-29