CH

Chin-Ching Huang

VT Vlsi Technology: 2 patents #12 of 143Top 9%
📍 Zhudong, CA: #1 of 1 inventorsTop 100%
Overall (1997): #44,083 of 185,788Top 25%
2
Patents 1997

Issued Patents 1997

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
5641988 Multi-layered, integrated circuit package having reduced parasitic noise characteristics Sang S. Lee, Ramachandra A. Rao, Fernand N. Forcier, Jr. 1997-06-24
5625225 Multi-layered, integrated circuit package having reduced parasitic noise characteristics Sang S. Lee, Ramachandra A. Rao, Fernand N. Forcier, Jr. 1997-04-29