Issued Patents 1997
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5674354 | Method for etching a conducting layer of the step-covered structure for semiconductor fabrication | Anna Su | 1997-10-07 |
| 5668394 | Prevention of fluorine-induced gate oxide degradation in WSi polycide structure | Cheng-Han Huang | 1997-09-16 |
| 5668393 | Locos technology with reduced junction leakage | Der-Yuan Wu, Jiunn Y. Wu | 1997-09-16 |
| 5665632 | Stress relaxation in dielectric before metalization | Edward Houn | 1997-09-09 |
| 5663599 | Metal layout pattern for improved passivation layer coverage | — | 1997-09-02 |
| 5661049 | Stress relaxation in dielectric before metallization | Edward Houn | 1997-08-26 |
| 5640041 | Stress relaxation in dielectric before metallization | Edward Houn | 1997-06-17 |
| 5633198 | Method of forming wiring with gaps in bend to improve electromigration resistance | Jiun-Yuan Wu | 1997-05-27 |
| 5633197 | Metallization to improve electromigration resistance by etching concavo-concave opening | Jiun-Yuan Wu | 1997-05-27 |
| 5612252 | Method of forming metallization to improve electromigration resistance | Jiun-Yuan Wu | 1997-03-18 |
| 5604148 | Process of fabricating stacked capacitor configuration for dynamic random access memory | — | 1997-02-18 |
| 5599746 | Method to eliminate polycide peeling at wafer edge using extended scribe lines | Der-Yuan Wu | 1997-02-04 |