Issued Patents 1997
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5698876 | Memory standard cell macro for semiconductor device | Tomoaki Yabe, Shinji Miyano, Kenji Numata | 1997-12-16 |
| 5659507 | Clock synchronous type DRAM with data latch | Tomoaki Yabe, Kenji Numata, Ryo Haga, Shinji Miyano, Tohru Furuyama | 1997-08-19 |
| 5640351 | Semiconductor memory circuit having data buses common to a plurality of memory cell arrays | Tomoaki Yabe, Shinji Miyano, Kenji Numata | 1997-06-17 |
| 5640365 | Semiconductor memory device with a decoding peripheral circuit for improving the operation frequency | Keniti Imamiya, Shinji Miyano, Tomoaki Yabe | 1997-06-17 |