Issued Patents 1997
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5701508 | Executing different instructions that cause different data type operations to be performed on single logical register file | Larry M. Mennemeier, Alexander Peleg, David Bistry, Millind Mittal, Carole Dulong +4 more | 1997-12-23 |
| 5694589 | Instruction breakpoint detection apparatus for use in an out-of-order microprocessor | Ashwani K. Gupta | 1997-12-02 |
| 5694574 | Method and apparatus for performing load operations in a computer system | Jeffery M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland | 1997-12-02 |
| 5687338 | Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor | Darrell D. Boggs, Robert P. Colwell, Michael A. Fetterman, Ashwani K. Gupta, Glenn J. Hinton +1 more | 1997-11-11 |
| 5680572 | Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers | Haitham Akkary, Jeffrey M. Abramson, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +2 more | 1997-10-21 |
| 5671444 | Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers | Haitham Akkary, Jeffrey M. Abramson, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +2 more | 1997-09-23 |
| 5664137 | Method and apparatus for executing and dispatching store operations in a computer system | Jeffrey M. Abramson, Haitham Akkary, Atig A. Bajwa, Michael A. Fetterman, Glenn J. Hinton +4 more | 1997-09-02 |
| 5636374 | Method and apparatus for performing operations based upon the addresses of microinstructions | Scott Dion Rodgers, Keshavan Tiruvallur, Michael W. Rhodehamel, Kris G. Konigsfeld, Haitham Akkary +2 more | 1997-06-03 |
| 5630075 | Write combining buffer for sequentially addressed partial line operations originating from a single instruction | Mandar Joshi, Nitin V. Sarangdhar | 1997-05-13 |
| 5627985 | Speculative and committed resource files in an out-of-order processor | Michael A. Fetterman, David B. Papworth, Glenn J. Hinton, Robert P. Colwell | 1997-05-06 |
| 5619664 | Processor with architecture for improved pipelining of arithmetic instructions by forwarding redundant intermediate data forms | — | 1997-04-08 |
| 5615385 | Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming | Michael A. Fetterman, Glenn J. Hinton, David B. Papworth, Robert P. Colwell | 1997-03-25 |
| 5613083 | Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions | Haitham Akkary, Glenn J. Hinton | 1997-03-18 |
| 5613132 | Integer and floating point register alias table within processor device | David W. Clift, James M. Arnold, Robert P. Colwell | 1997-03-18 |
| 5606670 | Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system | Jeffrey M. Abramson, Haitham Akkary, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland +1 more | 1997-02-25 |
| 5604878 | Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path | Robert P. Colwell, Michael A. Fetterman, Glenn J. Hinton, Robert W. Martell, David B. Papworth | 1997-02-18 |