EK

Edward Keyes

XD X Development: 19 patents #22 of 653Top 4%
SI Semiconductor Insights: 12 patents #2 of 23Top 9%
Google: 10 patents #2,552 of 22,993Top 15%
📍 Mountain View, CA: #362 of 11,022 inventorsTop 4%
🗺 California: #10,935 of 386,348 inventorsTop 3%
Overall (All Time): #76,377 of 4,157,543Top 2%
41
Patents All Time

Issued Patents All Time

Showing 26–41 of 41 patents

Patent #TitleCo-InventorsDate
9141194 Magnetometer-based gesture sensing with a wearable device Michael Patrick Johnson, Thad Eugene Starner 2015-09-22
8955973 Method and system for input detection using structured light projection Hayes Solos Raffle, Thad Eugene Starner, Josh Weaver 2015-02-17
8942419 Position estimation using predetermined patterns of light sources Bo Wu, Yong Zhao, Thad Eugene Starner, Hayes Solos Raffle 2015-01-27
8913789 Input methods and systems for eye positioning using plural glints Thad Eugene Starner, Yong Zhao, Joshua Weaver, Hayes Solos Raffle, Bo Wu 2014-12-16
8701058 Integrated circuit analysis systems and methods Vyacheslav Zavadsky 2014-04-15
8606041 Method of local tracing of connectivity and schematic representations produced therefrom Vyacheslav Zavadsky 2013-12-10
8347262 Method of deriving an integrated circuit schematic diagram Vyacheslav Zavadsky, Shane Michael Edmonds, Alexei E. Novikov 2013-01-01
8219940 Method and apparatus for removing dummy features from a data structure Mohammed Ouali, Jason Abt, Vyacheslav Zavadsky 2012-07-10
7886258 Method and apparatus for removing dummy features from a data structure Mohammed Ouali, Jason Abt, Vyacheslav Zavadsky 2011-02-08
7873203 Method of design analysis of existing integrated circuits Vyacheslav Zavadsky, Val Gont, Jason Abt, Stephen Begg 2011-01-18
7765517 Method and apparatus for removing dummy features from a data structure Mohammed Ouali, Jason Abt, Vyacheslav Zavadsky 2010-07-27
7693348 Method of registering and aligning multiple images Vyacheslav Zavadsky, Jason Abt, Mark Braverman, Vladimir Martincevic 2010-04-06
7643665 Method of design analysis of existing integrated circuits Vyacheslav Zavadsky, Val Gont, Jason Abt, Stephen Begg 2010-01-05
7580557 Method of design analysis of existing integrated circuits Vyacheslav Zavadsky, Val Gont, Jason Abt, Stephen Begg 2009-08-25
7278121 Method and apparatus for reducing redundant data in a layout data structure Elmehdi Aitnouri, Stephen Begg, Val Gont, Dale F. McIntyre, Mohammed Ouali +1 more 2007-10-02
7207018 Method and apparatus for locating short circuit faults in an integrated circuit layout Vyacheslav Zavadsky, Elmehdi Aitnouri, Jason Abt, Val Gont, Stephen Begg 2007-04-17