Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7873203 | Method of design analysis of existing integrated circuits | Vyacheslav Zavadsky, Edward Keyes, Jason Abt, Stephen Begg | 2011-01-18 |
| 7643665 | Method of design analysis of existing integrated circuits | Vyacheslav Zavadsky, Edward Keyes, Jason Abt, Stephen Begg | 2010-01-05 |
| 7580557 | Method of design analysis of existing integrated circuits | Vyacheslav Zavadsky, Edward Keyes, Jason Abt, Stephen Begg | 2009-08-25 |
| 7278121 | Method and apparatus for reducing redundant data in a layout data structure | Elmehdi Aitnouri, Edward Keyes, Stephen Begg, Dale F. McIntyre, Mohammed Ouali +1 more | 2007-10-02 |
| 7207018 | Method and apparatus for locating short circuit faults in an integrated circuit layout | Vyacheslav Zavadsky, Elmehdi Aitnouri, Edward Keyes, Jason Abt, Stephen Begg | 2007-04-17 |
| 7013028 | Advanced schematic editor | Jason Abt, Larry Lam | 2006-03-14 |
| 6738957 | Schematic organization tool | Jason Abt, Larry Lam, Alexei Ioudovski | 2004-05-18 |