Issued Patents All Time
Showing 51–73 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6159793 | Structure and fabricating method of stacked capacitor | — | 2000-12-12 |
| 6146968 | Method for forming a crown capacitor | Yii-Chian Lu, Shin-Puu Jeng | 2000-11-14 |
| 6143605 | Method for making a DRAM capacitor using a double layer of insitu doped polysilicon and undoped amorphous polysilicon with HSG polysilicon | — | 2000-11-07 |
| 6133088 | Method of forming crown-shaped capacitor | — | 2000-10-17 |
| 6117748 | Dishing free process for shallow trench isolation | Yeur-Luen Tu, Ko-Hsing Chang | 2000-09-12 |
| 6110826 | Dual damascene process using selective W CVD | Hsueh-Chung Chen | 2000-08-29 |
| 6107139 | Method for making a mushroom shaped DRAM capacitor | Yeur-Luen Tu | 2000-08-22 |
| 6100129 | Method for making fin-trench structured DRAM capacitor | Yeur-Luen Tu | 2000-08-08 |
| 6093590 | Method of fabricating transistor having a metal gate and a gate dielectric layer with a high dielectric constant | — | 2000-07-25 |
| 6090679 | Method for forming a crown capacitor | — | 2000-07-18 |
| 6090664 | Method for making a stacked DRAM capacitor | — | 2000-07-18 |
| 6074942 | Method for forming a dual damascene contact and interconnect | — | 2000-06-13 |
| 6074913 | Method for forming a DRAM capacitor | Yeur-Luen Tu | 2000-06-13 |
| 6048794 | Selective W CVD plug process with a RTA self-aligned W-silicide barrier layer | Hsueh-Chung Chen | 2000-04-11 |
| 6020265 | Method for forming a planar intermetal dielectric layer | — | 2000-02-01 |
| 5932487 | Method for forming a planar intermetal dielectric layer | Yeur-Luen Tu | 1999-08-03 |
| 5928961 | Dishing inhibited shallow trench isolation | Hseuh-Chung Chen | 1999-07-27 |
| 5916823 | Method for making dual damascene contact | Yeur-Luen Tu | 1999-06-29 |
| 5872045 | Method for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolation | Hsueh-Chung Chen | 1999-02-16 |
| 5827766 | Method for fabricating cylindrical capacitor for a memory cell | — | 1998-10-27 |
| 5759906 | Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits | — | 1998-06-02 |
| 5618747 | Process for producing a stacked capacitor having polysilicon with optimum hemispherical grains | — | 1997-04-08 |
| 5597754 | Increased surface area for DRAM, storage node capacitors, using a novel polysilicon deposition and anneal process | Yu-Hua Lee | 1997-01-28 |