Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9653552 | Body-tied, strained-channel multi-gate device and methods | Hong-Nien Lin, Horng-Chih Lin | 2017-05-16 |
| 9406800 | Body-tied, strained-channel multi-gate device and methods of manufacturing same | Hong-Nien Lin, Horng-Chih Lin | 2016-08-02 |
| 9214554 | Body-tied, strained-channel multi-gate device and methods of manufacturing same | Hong-Nien Lin, Horng-Chih Lin | 2015-12-15 |
| 8946811 | Body-tied, strained-channel multi-gate device and methods of manufacturing same | Hong-Nien Lin, Horng-Chih Lin | 2015-02-03 |
| 6894352 | Single-electron transistor and fabrication method thereof | Shu-Fen Hu, Yung-Chun Wu, Wen-Tai Lu, Shiue-Shin Liu, Tien-Sheng Chao | 2005-05-17 |
| 6667508 | Nonvolatile memory having a split gate | Horng-Chih Lin | 2003-12-23 |
| 6555424 | Thin film transistor with sub-gates and schottky source/drain and a manufacturing method of the same | Horng-Chih Lin, Ming-Shih Tsai | 2003-04-29 |
| 6495432 | Method of improving a dual gate CMOS transistor to resist the boron-penetrating effect | Chi-Chun Chen, Horng-Chih Lin, Chun-Yen Chang | 2002-12-17 |
| 6432786 | Method of forming a gate oxide layer with an improved ability to resist the process damage | Chi-Chun Chen, Horng-Chih Lin, Chun-Yen Chang | 2002-08-13 |
| 6232206 | Method for forming electrostatic discharge (ESD) protection transistors | Horng-Chih Lin | 2001-05-15 |
| 6087189 | Test structure for monitoring overetching of silicide during contact opening | — | 2000-07-11 |
| 5998246 | Self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain | Horng-Chih Lin | 1999-12-07 |
| 5893741 | Method for simultaneously forming local interconnect with silicided elevated source/drain MOSFET's | — | 1999-04-13 |
| 5827768 | Method for manufacturing an MOS transistor having a self-aligned and planarized raised source/drain structure | Horng-Chih Lin | 1998-10-27 |
| 5814544 | Forming a MOS transistor with a recessed channel | — | 1998-09-29 |
| 5783479 | Structure and method for manufacturing improved FETs having T-shaped gates | Horng-Chih Lin | 1998-07-21 |
| 5716860 | CMOS input buffer with NMOS gate coupled to Vss through undoped gate poly resistor | — | 1998-02-10 |
| 5618740 | Method of making CMOS output buffer with enhanced ESD resistance | — | 1997-04-08 |
| 5581105 | CMOS input buffer with NMOS gate coupled to V.sub.SS through undoped gate poly resistor | — | 1996-12-03 |
| 5529941 | Method for making an integrated circuit structure | — | 1996-06-25 |
| 5517049 | CMOS output buffer with enhanced ESD resistance | — | 1996-05-14 |
| 5510728 | Multi-finger input buffer with transistor gates capacitively coupled to ground | — | 1996-04-23 |
| 5418391 | Semiconductor-on-insulator integrated circuit with selectively thinned channel region | — | 1995-05-23 |
| 5413969 | Differential treatment to selectively avoid silicide formation on ESD I/O transistors in a salicide process | — | 1995-05-09 |
| 5394358 | SRAM memory cell with tri-level local interconnect | — | 1995-02-28 |