Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515878 | Semiconductor package with partial plating on contact side surfaces | Saravuth Sirinorakul, Woraya Benjasukul | 2019-12-24 |
| 10204850 | Semiconductor package with partial plating on contact side surfaces | Saravuth Sirinorakul, Woraya Benjavasukul | 2019-02-12 |
| 9947605 | Flip chip cavity package | Saravuth Sirinorakul | 2018-04-17 |
| 9899208 | Molded leadframe substrate semiconductor package | Saravuth Sirinorakul | 2018-02-20 |
| 9818676 | Singulation method for semiconductor package with plating on side of connectors | Saravuth Sirinorakul | 2017-11-14 |
| 9773722 | Semiconductor package with partial plating on contact side surfaces | Saravuth Sirinorakul, Woraya Benjavasukul | 2017-09-26 |
| 9761435 | Flip chip cavity package | Saravuth Sirinorakul | 2017-09-12 |
| 9741642 | Semiconductor package with partial plating on contact side surfaces | Saravuth Sirinorakul, Woraya Benjasukul | 2017-08-22 |
| 9711343 | Molded leadframe substrate semiconductor package | Saravuth Sirinorakul | 2017-07-18 |
| 9349679 | Singulation method for semiconductor package with plating on side of connectors | Saravuth Sirinorakul | 2016-05-24 |
| 9196470 | Molded leadframe substrate semiconductor package | Saravuth Sirinorakul | 2015-11-24 |
| 9099294 | Molded leadframe substrate semiconductor package | Saravuth Sirinorakul | 2015-08-04 |
| 9099317 | Method for forming lead frame land grid array | Saravuth Sirinorakul | 2015-08-04 |
| 9093486 | Molded leadframe substrate semiconductor package | Saravuth Sirinorakul | 2015-07-28 |
| 9082607 | Molded leadframe substrate semiconductor package | Saravuth Sirinorakul | 2015-07-14 |
| 8704381 | Very extremely thin semiconductor package | Saravuth Sirinorakul | 2014-04-22 |
| 8685794 | Lead frame land grid array with routing connector trace under unit | Saravuth Sirinorakul, Kasemsan Kongthaworn, Vorajit Suwannaset | 2014-04-01 |
| 8652879 | Lead frame ball grid array with traces under die | Saravuth Sirinorakul, Kasemsan Kongthaworn, Vorajit Suwannaset | 2014-02-18 |
| 8575762 | Very extremely thin semiconductor package | Saravuth Sirinorakul | 2013-11-05 |
| 8492906 | Lead frame ball grid array with traces under die | Saravuth Sirinorakul, Kasemsan Kongthaworn, Vorajit Suwannaset | 2013-07-23 |
| 8487451 | Lead frame land grid array with routing connector trace under unit | Saravuth Sirinorakul, Kasemsan Kongthaworn, Vorajit Suwannaset | 2013-07-16 |
| 8338922 | Molded leadframe substrate semiconductor package | Saravuth Sirinorakul | 2012-12-25 |
| 8129229 | Method of manufacturing semiconductor package containing flip-chip arrangement | Saravuth Sirinorakul | 2012-03-06 |
| 8125077 | Package with heat transfer | Saravuth Sirinorakul | 2012-02-28 |
| 8071426 | Method and apparatus for no lead semiconductor package | Saravuth Sirinorakul | 2011-12-06 |