Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10374791 | Method of protecting electronic circuit against eavesdropping by power analysis and electronic circuit using the same | Nir Tasher | 2019-08-06 |
| 10019571 | Protection from side-channel attacks by varying clock delays | Uri Kaluzhny | 2018-07-10 |
| 9846187 | Snooping detection between silicon elements in a circuit | — | 2017-12-19 |
| 9819657 | Protection of memory interface | Nir Tasher, Moshe Alon, Ziv Hershman, Uri Kaluzhny | 2017-11-14 |
| 9703945 | Secured computing system with asynchronous authentication | Ziv Hershman, Moshe Alon | 2017-07-11 |
| 9697310 | Level faults interception in integrated circuits | — | 2017-07-04 |
| 9523722 | Method and apparatus for supply voltage glitch detection in a monolithic integrated circuit device | Nir Tasher, Dennis Chin Cheng, Koying Huang | 2016-12-20 |
| 9471413 | Memory device with secure test mode | Nir Tasher, Uri Kaluzhny, Tsachi Weiser | 2016-10-18 |
| 9455962 | Protecting memory interface | Nir Tasher, Moshe Alon, Ziv Hershman, Uri Kaluzhny | 2016-09-27 |
| 9397663 | Fault protection for high-fanout signal distribution circuitry | Nir Tasher, Leonid Azriel | 2016-07-19 |
| 9343162 | Protection against side-channel attacks on non-volatile memory | Nir Tasher, Dennis Chin Cheng, Boaz Tabachnik | 2016-05-17 |
| 9318221 | Memory device with secure test mode | Nir Tasher, Uri Kaluzhny, Tsachi Weiser | 2016-04-19 |
| 9223960 | State-machine clock tampering detection | Uri Kaluzhny, Tsachi Weiser, Nir Tasher | 2015-12-29 |
| 7398554 | Secure lock mechanism based on a lock word | Ohad Falik, Ilan Margalit | 2008-07-08 |