| 12153807 |
Memory segmentation with substitution |
Nir Tasher, Itay Admon, Mark Luko |
2024-11-26 |
| 12105860 |
Flash programming randomization |
— |
2024-10-01 |
| 12105991 |
Mapping for storing data and metadata |
— |
2024-10-01 |
| 11907559 |
Physically secure memory partitioning |
Itay Admon, Nir Tasher |
2024-02-20 |
| 10951403 |
Updating cryptographic keys stored in non-volatile memory |
Mark Luko |
2021-03-16 |
| 10445001 |
Memory control scheme for flash memory devices |
Hezi Pereg |
2019-10-15 |
| 10133554 |
Non-modular multiplier, method for non-modular multiplication and computational device |
— |
2018-11-20 |
| 10057064 |
Computational method, computational device and computer software product for montgomery domain |
— |
2018-08-21 |
| 10037441 |
Bus protection with improved key entropy |
Nir Tasher |
2018-07-31 |
| 10019571 |
Protection from side-channel attacks by varying clock delays |
Valery Teper |
2018-07-10 |
| 9857988 |
Data management in multiply-writeable flash memories |
— |
2018-01-02 |
| 9819657 |
Protection of memory interface |
Nir Tasher, Moshe Alon, Valery Teper, Ziv Hershman |
2017-11-14 |
| 9641491 |
Secure memory interface with cumulative authentication |
Nir Tasher |
2017-05-02 |
| 9626529 |
Secure data storage device and data writing and read methods thereof |
Nir Tasher, Mark Luko |
2017-04-18 |
| 9471413 |
Memory device with secure test mode |
Nir Tasher, Tsachi Weiser, Valery Teper |
2016-10-18 |
| 9455962 |
Protecting memory interface |
Nir Tasher, Moshe Alon, Valery Teper, Ziv Hershman |
2016-09-27 |
| 9318221 |
Memory device with secure test mode |
Nir Tasher, Tsachi Weiser, Valery Teper |
2016-04-19 |
| 9269454 |
Counter using one-time-programmable memory |
David Harbater |
2016-02-23 |
| 9223960 |
State-machine clock tampering detection |
Tsachi Weiser, Valery Teper, Nir Tasher |
2015-12-29 |
| 8984631 |
Processor with differential power analysis attack protection |
— |
2015-03-17 |
| 8621186 |
Obfuscated hardware multi-threading |
David Darmon |
2013-12-31 |
| 8266194 |
Linear feedback shift registers with XOR logic gates including a bit generator to control movement along stages |
— |
2012-09-11 |