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Semiconductor structure |
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Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage |
Rong-Ching Chen, Ching-Chun Huang |
2013-04-16 |
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Method for fabricating integrated circuits having both high voltage and low voltage devices |
Jung-Ching Chen, Sheng-Hsiung Yang, Jim Su |
2007-08-14 |
| 7091079 |
Method of forming devices having three different operation voltages |
Jung-Ching Chen |
2006-08-15 |
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Method of integrating high voltage metal oxide semiconductor devices and submicron metal oxide semiconductor devices |
Ching-Chun Huang, Ming-Hsien Huang, Rong-Ching Chen |
2006-02-28 |
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Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage |
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2005-05-31 |
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Multi-film capping layer for a salicide process |
Ming-Shing Chen, Shu-Jen Chen, Kuen-Syh Tseng |
2002-10-08 |
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Fabrication method of an interconnect |
— |
2000-12-26 |
| 6150916 |
Architecture of poly fuses |
Tsan-Wen Liu |
2000-11-21 |
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Method of manufacturing interconnect |
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2000-10-17 |
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Method of forming unlanded via hole |
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2000-07-04 |