Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6638841 | Method for reducing gate length bias | Kai-Jen Ko, Yuan-Li Tsai, Ming H. Wu, Steven Huang | 2003-10-28 |
| 6624079 | Method for forming high resistance resistor with integrated high voltage device process | Yuan-Li Tsai, Marcus Yang, Ralph Chen, Heng-Chun Kao | 2003-09-23 |
| 6410377 | Method for integrating CMOS sensor and high voltage device | Sheng-Hsiung Yang | 2002-06-25 |
| 6268266 | Method for forming enhanced FOX region of low voltage device in high voltage process | Fei Chen, Meng-Jin Tsai, Wei-Chung Chen | 2001-07-31 |
| 6204129 | Method for producing a high-voltage and low-voltage MOS transistor with salicide structure | Wei-Chung Chen, Chien-Kuo Yang | 2001-03-20 |
| 6117718 | Method for forming BJT via formulation of high voltage device in ULSI | Sheng-Hsiung Yang | 2000-09-12 |