Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5429976 | Self-aligned method for forming polysilicon word lines on top of gate electrodes to increase capacitance of a stacked capacitor in a DRAM cell | Gary Hong | 1995-07-04 |
| 5418176 | Process for producing memory devices having narrow buried N+ lines | Ming-Tzong Yang, Chen-Chiu Hsue | 1995-05-23 |
| 5393704 | Self-aligned trenched contact (satc) process | Water Lur | 1995-02-28 |
| 5384268 | Charge damage free implantation by introduction of a thin conductive layer | Water Lur, Ben Chen | 1995-01-24 |
| 5374586 | Multi-LOCOS (local oxidation of silicon) isolation process | Water Lur | 1994-12-20 |
| 5371036 | Locos technology with narrow silicon trench | Water Lur | 1994-12-06 |
| 5364817 | Tungsten-plug process | Water Lur, Shih-Chanh Chang, Liang Chih Lin | 1994-11-15 |
| 5364803 | Method of preventing fluorine-induced gate oxide degradation in WSi.sub.x polycide structure | Water Lur | 1994-11-15 |
| 5308787 | Uniform field oxidation for locos isolation | Gary Hong, Hong-Tsz Pan | 1994-05-03 |
| 5130266 | Polycide gate MOSFET process for integrated circuits | Water Lur | 1992-07-14 |
| 5115296 | Preferential oxidization self-aligned contact technology | Chen-Chiu Hsue | 1992-05-19 |