TN

Tetsuya Nakagawa

TO Toyota: 26 patents #728 of 26,838Top 3%
HI Hitachi: 20 patents #1,757 of 28,497Top 7%
KY Kyulux: 4 patents #21 of 91Top 25%
SS Sumitomo Wiring Systems: 4 patents #805 of 2,615Top 35%
RT Renesas Technology: 4 patents #758 of 3,337Top 25%
AT Autonetworks Technologies: 3 patents #449 of 1,079Top 45%
HE Hitachi Vlsi Engineering: 3 patents #237 of 666Top 40%
RE Renesas Electronics: 3 patents #1,322 of 4,529Top 30%
Sumitomo Electric Industries: 3 patents #7,735 of 21,551Top 40%
HA Hitachi America: 2 patents #27 of 97Top 30%
Mitsubishi Electric: 2 patents #11,187 of 25,717Top 45%
NU National University: 1 patents #4 of 70Top 6%
NT NTT: 1 patents #2,911 of 4,871Top 60%
YC Yanmar Holdings Co.: 1 patents #349 of 636Top 55%
HE Hitachi Micro Computer Engineering: 1 patents #131 of 393Top 35%
HM Hitachi Maxell: 1 patents #659 of 1,211Top 55%
HC Hodogaya Chemical Co.: 1 patents #201 of 359Top 60%
KU Kyushu University, National University: 1 patents #221 of 767Top 30%
HE Hitachi, Vlsi Eng.: 1 patents #1 of 28Top 4%
NT Nara Institute Of Science And Technology: 1 patents #13 of 65Top 20%
📍 Yokohama, CA: #56 of 287 inventorsTop 20%
Overall (All Time): #29,418 of 4,157,543Top 1%
70
Patents All Time

Issued Patents All Time

Showing 51–70 of 70 patents

Patent #TitleCo-InventorsDate
6064471 Distance measuring device 2000-05-16
5987556 Data processing device having accelerator for digital signal processing Haruyasu Okubo, Atsushi Kiuchi 1999-11-16
5854636 Semiconductor IC with a plurality of processing circuits which receive parallel data via a parallel data transfer circuit Takao Watanabe, Yoshinobu Nakagome, Kazuo Ishikura, Atsushi Kiuchi 1998-12-29
5854997 Electronic interpreter utilizing linked sets of sentences Hiroko Sukeda, Yoshiyuki Kaneko, Muneaki Yamaguchi, Toshihisa Tsukada 1998-12-29
5745050 Obstacle detection apparatus for vehicles 1998-04-28
5638524 Digital signal processor and method for executing DSP and RISC class instructions defining identical data processing or data transfer operations Atsushi Kiuchi, Toru Baji, Kenji Kaneko 1997-06-10
5579493 System with loop buffer and repeat control circuit having stack for storing control information Atsushi Kiuchi 1996-11-26
5535410 Parallel processor having decoder for selecting switch from the group of switches and concurrently inputting MIMD instructions while performing SIMD operation Takao Watanabe, Yoshinobu Nakagome 1996-07-09
5430885 Multi-processor system and co-processor used for the same Kenji Kaneko, Hirotada Ueda, Atsuchi Kiuchi, Yoshimune Hagiwara, You Takamori +1 more 1995-07-04
5426745 Apparatus including a pair of neural networks having disparate functions cooperating to perform instruction recognition Toru Baji, Kouki Noguchi, Motonobu Tonomura, Hajime Akimoto, Toshiaki Masuhara 1995-06-20
5426600 Double precision division circuit and method for digital signal processor Atsushi Kiuchi 1995-06-20
5241679 Data processor for executing data saving and restoration register and data saving stack with corresponding stack storage for each register Masafumi Miyamoto, Yasuhiro Sagesaka, Toru Baji 1993-08-31
5163111 Customized personal terminal device Toru Baji, Kouki Noguchi, Motonobu Tonomura, Hajime Akimoto, Toshiaki Masuhara 1992-11-10
5148387 Logic circuit and data processing apparatus using the same Kazuo Yano, Koichiro Ishibashi, Katsuhiro Shimohigashi, Osamu Minato 1992-09-15
5027400 Multimedia bidirectional broadcast system Toru Baji, Yukio Nakano, Shiro Tanabe, Hirotsugu Kojima 1991-06-25
4958276 Single chip processor Atsushi Kiuchi, Kenji Kaneko, Jun Ishida, Yoshimune Hagiwara, Takashi Akazawa +1 more 1990-09-18
4910466 Selecting means for selecting a plurality of information Atsushi Kiuchi, Jun Ishida, Kenji Kaneko, Tomoru Sato, Shigeki Masumura +2 more 1990-03-20
4809206 Information processing apparatus Atsushi Kiuchi, Kenji Kaneko, Jun Ishida, Yoshimune Hagiwara, Hirotada Ueda 1989-02-28
4752905 High-speed multiplier having carry-save adder circuit Kenji Kaneko, Yoshimune Hagiwara, Hitoshi Matsushima, Hirotada Ueda 1988-06-21
4745581 LSI system of a structure requiring no additional address signals to incorporate additional status registers into the system Tomoru Sato, Kenji Kaneko, Hirotada Ueda, Yoshimune Hagiwara, Hitoshi Matsushima +1 more 1988-05-17