Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5428236 | Semiconductor memory device having trenched capicitor | — | 1995-06-27 |
| 5185567 | Power circuit for an LSI | — | 1993-02-09 |
| 4970688 | Memory device having operating function | Tsutomu Minagawa, Naoyuki Kai, Masahide Ohhashi | 1990-11-13 |
| 4837460 | Complementary MOS circuit having decreased parasitic capacitance | — | 1989-06-06 |
| 4814853 | Semiconductor device with programmable fuse | — | 1989-03-21 |
| 4794571 | Dynamic read-write random access memory | — | 1988-12-27 |
| 4792834 | Semiconductor memory device with buried layer under groove capacitor | — | 1988-12-20 |
| 4723155 | Semiconductor device having a programmable fuse element | — | 1988-02-02 |
| 4710905 | Semiconductor memory device | — | 1987-12-01 |
| 4697252 | Dynamic type semiconductor memory device | Tohru Furuyama | 1987-09-29 |
| 4641165 | Dynamic memory device with an RC circuit for inhibiting the effects of alpha particle radiation | Tetsuya Iizuka, Syuso Fujii | 1987-02-03 |
| 4608666 | Semiconductor memory | — | 1986-08-26 |
| 4585955 | Internally regulated power voltage circuit for MIS semiconductor integrated circuit | — | 1986-04-29 |
| 4532607 | Programmable circuit including a latch to store a fuse's state | — | 1985-07-30 |
| 4517583 | Semiconductor integrated circuit including a fuse element | — | 1985-05-14 |
| 4489339 | SOS MOSFET With self-aligned channel contact | — | 1984-12-18 |
| 4484209 | SOS Mosfet with thinned channel contact region | — | 1984-11-20 |
| 4479202 | CMOS Sense amplifier | — | 1984-10-23 |
| 4467452 | Nonvolatile semiconductor memory device and method of fabricating the same | Shozo Saito, Kazuhiko Hashimoto, Norio Endo | 1984-08-21 |
| 4453234 | Nonvolatile semiconductor memory device | — | 1984-06-05 |
| 4432610 | Liquid crystal display device | Hiroshi Kobayashi, Hisashi Yamada | 1984-02-21 |
| 4385308 | Non-volatile semiconductor memory device | — | 1983-05-24 |
| 4327368 | CMOS Transistor pair with reverse biased substrate to prevent latch-up | — | 1982-04-27 |
| 4287574 | Memory cell with non-volatile memory elements | — | 1981-09-01 |
| 4236170 | Gate controlled negative resistance semiconductor device | — | 1980-11-25 |