Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11601119 | Radiation hardened flip-flop circuit for mitigating single event transients | Salim A. Rabaa, Ethan H. Cannon | 2023-03-07 |
| 11029355 | Direct measurement test structures for measuring static random access memory static noise margin | Mark Gang Yao, Ethan H. Cannon | 2021-06-08 |
| 10734998 | Complementary self-limiting logic | Jeff Maharrey, Salim A. Rabaa | 2020-08-04 |
| 10705552 | Self-optimizing circuits for mitigating total ionizing dose effects, temperature drifts, and aging phenomena in fully-depleted silicon-on-insulator technologies | Alfio Zanchi, Jeffrey Maharrey, Roger Brees | 2020-07-07 |
| 9013219 | Filtered radiation hardened flip flop with reduced power consumption | Ethan H. Cannon, Salim A. Rabaa | 2015-04-21 |
| 8754701 | Interleaved transient filter | Ethan H. Cannon, Salim A. Rabaa | 2014-06-17 |
| 8207753 | Method and apparatus for reducing radiation and cross-talk induced data errors | Ethan H. Cannon, Salim A. Rabaa | 2012-06-26 |
| 8054099 | Method and apparatus for reducing radiation and cross-talk induced data errors | Ethan H. Cannon, Salim A. Rabaa | 2011-11-08 |
| 7215581 | Triple redundant latch design with low delay time | Jonathan Lotz, Daniel Krueger | 2007-05-08 |
| 7179690 | High reliability triple redundant latch with voting logic on each storage node | Jonathan Lotz, Daniel Krueger | 2007-02-20 |
| 7054203 | High reliability memory element with improved delay time | Jonathan Lotz, Daniel Krueger | 2006-05-30 |
| 6937527 | High reliability triple redundant latch with voting logic on each storage node | Jonathan Lotz, Daniel Krueger | 2005-08-30 |
| 6930527 | Triple redundant latch design with storage node recovery | Daniel Krueger, Jonathan Lotz | 2005-08-16 |
| 6882201 | Triple redundant latch design using a fail-over mechanism with backup | Kenneth Koch, II, Daniel Krueger | 2005-04-19 |