Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6797563 | Method of forming cross point type DRAM cell | Hiroyuki Yoshida | 2004-09-28 |
| 6657308 | Method for forming a self-aligned contact | — | 2003-12-02 |
| 6580112 | Method for fabricating an open can-type stacked capacitor on an uneven surface | Masayuki Moroi, Katsushi Boku, Toshiyuki Nagata | 2003-06-17 |
| 6563155 | Cross point type DRAM cell composed of a pillar having an active region | Hiroyuki Yoshida | 2003-05-13 |
| 6434063 | Method of repairing semiconductor memory, electron-beam memory repairing apparatus and redundancy memory circuit to which the method of repairing semiconductor memory is applicable | Naoki Nishio, Hideyuki Fukuhara, Yoshinobu Kagawa | 2002-08-13 |
| 6362506 | Minimization-feasible word line structure for DRAM cell | — | 2002-03-26 |
| 6291293 | Method for fabricating an open can-type stacked capacitor on an uneven surface | Masayuki Moroi, Katsushi Boku, Toshiyuki Nagata | 2001-09-18 |
| 6245664 | Method and system of interconnecting conductive elements in an integrated circuit | — | 2001-06-12 |
| 6204118 | Method for fabrication an open can-type stacked capacitor on local topology | Masayuki Moroi, Katsushi Boku | 2001-03-20 |
| 6184080 | Method of the simultaneous formation for the storage node contacts, bit line contacts, and the contacts for periphery circuits | — | 2001-02-06 |
| 6004870 | Method for forming a self-aligned contact | — | 1999-12-21 |
| 5985677 | Method of repairing semiconductor memory, electron-beam memory repairing apparatus and redundancy memory circuit to which the method of repairing semiconductor memory is applicable | Naoki Nishio, Hideyuki Fukuhara, Yoshinobu Kagawa | 1999-11-16 |
| 5861649 | Trench-type semiconductor memory device | Hiroyuki Yoshida, Takayuki Niuya, Toshiyuki Nagata, Yoshihiro Ogata | 1999-01-19 |
| 5754432 | Apparatus and method for estimating chip yield | Takao Komatsuzaki, Hideyuki Fukuhara | 1998-05-19 |
| 5734184 | DRAM COB bit line and moat arrangement | Katsuyoshi Andoh, Masayuki Moroi, Katsushi Boku | 1998-03-31 |
| 5641701 | Method for fabricating a semiconductor device with laser programable fuses | Hideyuki Fukuhara, David J. McElroy | 1997-06-24 |
| 5618750 | Method of making fuse with non-corrosive termination of corrosive fuse material | Hideyuki Fukuhara | 1997-04-08 |
| 5610100 | Method for concurrently forming holes for interconnection between different conductive layers and a substrate element or circuit element close to the substrate surface | Hiroyuki Kurino | 1997-03-11 |
| 5514628 | Two-step sinter method utilized in conjunction with memory cell replacement by redundancies | Osaomi Enomoto, Yoshihiro Ogata, Yoshinobu Yoneoka | 1996-05-07 |
| 5470778 | Method of manufacturing a semiconductor device | Toshiyuki Nagata, Hiroyuki Yoshida, Takayuki Niuya, Yoshihiro Ogata, Katsushi Boku | 1995-11-28 |
| 5317177 | Semiconductor device and method of manufacturing the same | Toshiyuki Nagata, Hiroyuki Yoshida, Takayuki Niuya, Yoshihiro Ogata, Katsushi Boku | 1994-05-31 |